This application is based upon and claims priority from prior French Patent Application No. 01 03794, filed on Mar. 21, 2001, the entire disclosure of which is herein incorporated by reference.
1. Field of the Invention
The present invention relates to a sinusoidal signal multiplier circuit. The invention can be applied, for example, in the field of analog FM demodulators.
2. Description of the Related Art
The multiplier circuits commonly used to multiply sinusoidal signals are asymmetrical cells showing a phase shift between their inputs. An asymmetrical multiplication cell may be modelled in the form of a perfect, two-input multiplier circuit having, at each of its inputs, an element that introduces a phase delay. A modelling of this kind is shown in FIG. 1. The multiplication cell, referenced C, has two inputs E1 and E2 receiving sinusoidal signals, S1(t) and S2(t), and one output S delivering a sinusoidal signal O(t). In this cell, the input signals S1(t) and S2(t) are phase-shifted by phase delay elements, respectively introducing a phase delay (xcfx861 and xcfx862, and are then multiplied by a perfect multiplier. If the inputs E1 and E2 of the multiplication cell respectively are provided with the signals S1(t)=A1*cos(wt) and S2(t)=A2*sin(wt), the following signal O(t) is obtained at the output of the multiplication cell:                               O          ⁡                      (            t            )                          =                ⁢                              A            1                    ⁢                      A            2                    *                      cos            ⁡                          (                                                w                  ⁢                                      xe2x80x83                                    ⁢                  t                                -                                  ϕ                  ⁢                  1                                            )                                *                      sin            ⁡                          (                                                w                  ⁢                                      xe2x80x83                                    ⁢                  t                                -                                  ϕ                  ⁢                  2                                            )                                                              =                ⁢                                            (                                                A                  1                                ⁢                                                      A                    2                                    /                  2                                            )                        *                          sin              ⁡                              (                                                      2                    ⁢                    w                    ⁢                                          xe2x80x83                                        ⁢                    t                                    -                                      ϕ                    ⁢                    1                                    -                                      ϕ                    ⁢                    2                                                  )                                              +                                    (                                                A                  1                                ⁢                                                      A                    2                                    /                  2                                            )                        *                          sin              ⁡                              (                                                      ϕ                    ⁢                    1                                    -                                      ϕ                    ⁢                    2                                                  )                                                        
The output signal O(t) comprises a sinusoidal component (A1A2/2)*sin(2wtxe2x88x92xcfx861xe2x88x92xcfx862) and a DC component (A1A2/2)*sin(xcfx861xe2x88x92xcfx862) corresponding to an amplitude offset of the output signal. This additional DC component in the output signal O(t) is undesirable for many applications.
Accordingly, there exists a need for overcoming the disadvantages of the prior art as discussed above.
It is an aim of the present invention to provide a multiplier circuit capable of delivering an output signal substantially without any DC component.
An aspect of the present invention therefore is a sinusoidal signal multiplier circuit capable of producing an output sinusoidal signal substantially without any DC component, comprising a first multiplication cell receiving a first sinusoidal signal at a first input and a second sinusoidal signal at a second input, the first multiplication cell delivering a first output signal, and the sinusoidal signal multiplier circuit furthermore comprising: a second multiplication cell identical to the first multiplication cell receiving the second sinusoidal signal at its first input and the first sinusoidal signal at its second input, and delivering a second output signal, and an adder circuit to add the first output signal and the second output signal in order to generate from the sinusoidal signal multiplier circuit an output signal that is substantially without any DC component.